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Texas Instruments /MSP432P401R /SystemControlSpace /ACTLR

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Interpret as ACTLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISMCYCINT)DISMCYCINT 0 (DISDEFWBUF)DISDEFWBUF 0 (DISFOLD)DISFOLD 0 (DISFPCA)DISFPCA 0 (DISOOFP)DISOOFP

Description

Auxiliary Control Register

Fields

DISMCYCINT

Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs.
DISDEFWBUF

Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed.
DISFOLD

Disables IT folding.
DISFPCA

Disable automatic update of CONTROL.FPCA
DISOOFP

Disables floating point instructions completing out of order with respect to integer

instructions.

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data